[PATCH] Initial support for Neuros OSD2 platform.

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[PATCH] Initial support for Neuros OSD2 platform.

A. Porodko
The Neuros OSD 2.0 is the hardware component of the Neuros Open
Internet Television Platform. Hardware is very close to Ti DM644X-EVM board.
It has: DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
Additionaly realtime clock, IR remote control receiver,
IR Blaster based on MSP430 (firmware although is different
from used in DM644X-EVM), internal ATA-6 3.5? HDD drive
with PATA interface, two muxed red-green leds.

For more information please refer to
        http://wiki.neurostechnology.com/index.php/OSD_2.0_HD

Signed-off-by: Andrey Porodko <[hidden email]>
---
 arch/arm/mach-davinci/Kconfig             |    7 +
 arch/arm/mach-davinci/Makefile            |    1 +
 arch/arm/mach-davinci/board-neuros-osd2.c |  306 +++++++++++++++++++++++++++++
 arch/arm/mach-davinci/dm644x.c            |    5 +
 arch/arm/mach-davinci/include/mach/mux.h  |    5 +
 5 files changed, 324 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-davinci/board-neuros-osd2.c

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 89d5aa7..033bfed 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -65,6 +65,13 @@ config MACH_SFFSDR
   Say Y here to select the Lyrtech Small Form Factor
   Software Defined Radio (SFFSDR) board.
 
+config MACH_NEUROS_OSD2
+ bool "Neuros OSD2 Open Television Set Top Box"
+ depends on ARCH_DAVINCI_DM644x
+ help
+  Configure this option to specify the whether the board used
+  for development is a Neuros OSD2 Open Set Top Box.
+
 config MACH_DAVINCI_DM355_EVM
  bool "TI DM355 EVM"
  default ARCH_DAVINCI_DM355
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 5eae1a9..eeb9230 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_CP_INTC) += cp_intc.o
 # Board specific
 obj-$(CONFIG_MACH_DAVINCI_EVM)   += board-dm644x-evm.o
 obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
+obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o
 obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
 obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o
 obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
new file mode 100644
index 0000000..d0a1462
--- /dev/null
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -0,0 +1,306 @@
+/*
+ * Neuros Technologies OSD2 board support
+ *
+ * Modified from original 644X-EVM board support.
+ * 2008 (c) Neuros Technology, LLC.
+ * 2009 (c) Jorge Luis Zapata Muga <[hidden email]>
+ * 2009 (c) Andrey A. Porodko <[hidden email]>
+ *
+ * The Neuros OSD 2.0 is the hardware component of the Neuros Open
+ * Internet Television Platform. Hardware is very close to Ti
+ * DM644X-EVM board. It has:
+ * DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
+ * USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
+ * Additionaly realtime clock, IR remote control receiver,
+ * IR Blaster based on MSP430 (firmware although is different
+ * from used in DM644X-EVM), internal ATA-6 3.5? HDD drive
+ * with PATA interface, two muxed red-green leds.
+ *
+ * For more information please refer to
+ * http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
+ *
+ * 10/2009 Initial code with nand flash, fb, ide, ethernet, leds-gpio,
+ * usb support.
+ */
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/dm644x.h>
+#include <mach/i2c.h>
+#include <mach/serial.h>
+#include <mach/mux.h>
+#include <mach/nand.h>
+#include <mach/mmc.h>
+#include <mach/usb.h>
+
+#define NEUROS_OSD2_PHY_MASK (0x2)
+#define NEUROS_OSD2_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
+
+#define DAVINCI_CFC_ATA_BASE 0x01C66000
+
+#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
+
+#define LXT971_PHY_ID (0x001378e2)
+#define LXT971_PHY_MASK (0xfffffff0)
+
+#define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
+#define NTOSD2_MSP430_I2C_ADDR 0x59
+#define NTOSD2_MSP430_IRQ 2
+
+/* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
+ * 2048 blocks in the device, 64 pages per block, 2048 bytes per
+ * page.
+ */
+
+#define NAND_BLOCK_SIZE SZ_128K
+
+struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
+ {
+ /* UBL (a few copies) plus U-Boot */
+ .name = "bootloader",
+ .offset = 0,
+ .size = 15 * NAND_BLOCK_SIZE,
+ .mask_flags = MTD_WRITEABLE, /* force read-only */
+ }, {
+ /* U-Boot environment */
+ .name = "params",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 1 * NAND_BLOCK_SIZE,
+ .mask_flags = 0,
+ }, {
+ /* Kernel */
+ .name = "kernel",
+ .offset = MTDPART_OFS_APPEND,
+ .size = SZ_4M,
+ .mask_flags = 0,
+ }, {
+ /* File System */
+ .name = "filesystem",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ .mask_flags = 0,
+ }
+ /* A few blocks at end hold a flash Bad Block Table. */
+};
+
+static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
+ .parts = davinci_ntosd2_nandflash_partition,
+ .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
+ .ecc_mode = NAND_ECC_HW,
+ .options = NAND_USE_FLASH_BBT,
+};
+
+static struct resource davinci_ntosd2_nandflash_resource[] = {
+ {
+ .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
+ .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
+ .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device davinci_ntosd2_nandflash_device = {
+ .name = "davinci_nand",
+ .id = 0,
+ .dev = {
+ .platform_data = &davinci_ntosd2_nandflash_data,
+ },
+ .num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
+ .resource = davinci_ntosd2_nandflash_resource,
+};
+
+static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device davinci_fb_device = {
+ .name = "davincifb",
+ .id = -1,
+ .dev = {
+ .dma_mask = &davinci_fb_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = 0,
+};
+
+static struct resource ide_resources[] = {
+ {
+ .start = DAVINCI_CFC_ATA_BASE,
+ .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_IDE,
+ .end = IRQ_IDE,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 ide_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device ide_dev = {
+ .name = "palm_bk3710",
+ .id = -1,
+ .resource = ide_resources,
+ .num_resources = ARRAY_SIZE(ide_resources),
+ .dev = {
+ .dma_mask = &ide_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+static struct snd_platform_data dm644x_ntosd2_snd_data;
+
+static struct gpio_led ntosd2_leds[] = {
+ { .name = "led1_green", .gpio = GPIO(10), },
+ { .name = "led1_red",   .gpio = GPIO(11), },
+ { .name = "led2_green", .gpio = GPIO(12), },
+ { .name = "led2_red",   .gpio = GPIO(13), },
+};
+
+static struct gpio_led_platform_data ntosd2_leds_data = {
+ .num_leds = ARRAY_SIZE(ntosd2_leds),
+ .leds = ntosd2_leds,
+};
+
+static struct platform_device ntosd2_leds_dev = {
+ .name = "leds-gpio",
+ .id   = -1,
+ .dev = {
+ .platform_data = &ntosd2_leds_data,
+ },
+};
+
+
+static struct platform_device *davinci_ntosd2_devices[] __initdata = {
+ &davinci_fb_device,
+ &ntosd2_leds_dev,
+};
+
+static struct davinci_uart_config uart_config __initdata = {
+ .enabled_uarts = (1 << 0),
+};
+
+static void __init
+davinci_ntosd2_map_io(void)
+{
+ dm644x_init();
+}
+
+/*
+ I2C initilization
+*/
+static struct davinci_i2c_platform_data ntosd2_i2c_pdata = {
+ .bus_freq = 20 /* kHz */,
+ .bus_delay = 100 /* usec */,
+};
+
+static struct i2c_board_info __initdata ntosd2_i2c_info[] =  {
+};
+
+static void __init ntosd2_init_i2c(void)
+{
+ davinci_init_i2c(&ntosd2_i2c_pdata);
+ gpio_request(NTOSD2_MSP430_IRQ, ntosd2_i2c_info[0].type);
+ gpio_direction_input(NTOSD2_MSP430_IRQ);
+ ntosd2_i2c_info[0].irq = gpio_to_irq(NTOSD2_MSP430_IRQ);
+ i2c_register_board_info(1, ntosd2_i2c_info,
+ ARRAY_SIZE(ntosd2_i2c_info));
+}
+
+static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
+ .wires = 4,
+ .version = MMC_CTLR_VERSION_1
+};
+
+
+#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
+ defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
+#define HAS_ATA 1
+#else
+#define HAS_ATA 0
+#endif
+
+#if defined(CONFIG_MTD_NAND_DAVINCI) || \
+ defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
+#define HAS_NAND 1
+#else
+#define HAS_NAND 0
+#endif
+
+static __init void davinci_ntosd2_init(void)
+{
+ struct clk *aemif_clk;
+ struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+ aemif_clk = clk_get(NULL, "aemif");
+ clk_enable(aemif_clk);
+
+ if (HAS_ATA) {
+ if (HAS_NAND)
+ pr_warning("WARNING: both IDE and Flash are "
+ "enabled, but they share AEMIF pins.\n"
+ "\tDisable IDE for NAND/NOR support.\n");
+ davinci_cfg_reg(DM644X_HPIEN_DISABLE);
+ davinci_cfg_reg(DM644X_ATAEN);
+ davinci_cfg_reg(DM644X_HDIREN);
+ platform_device_register(&ide_dev);
+ } else if (HAS_NAND) {
+ davinci_cfg_reg(DM644X_HPIEN_DISABLE);
+ davinci_cfg_reg(DM644X_ATAEN_DISABLE);
+
+ /* only one device will be jumpered and detected */
+ if (HAS_NAND)
+ platform_device_register(
+ &davinci_ntosd2_nandflash_device);
+ }
+
+ platform_add_devices(davinci_ntosd2_devices,
+ ARRAY_SIZE(davinci_ntosd2_devices));
+
+ /* Initialize I2C interface specific for this board */
+ ntosd2_init_i2c();
+
+ davinci_serial_init(&uart_config);
+ dm644x_init_asp(&dm644x_ntosd2_snd_data);
+
+ soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK;
+ soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;
+
+ davinci_setup_usb(1000, 8);
+ /* Mux the pins to be GPIOS, VLYNQEN is already done at startup */
+ /* The AEAWx. are five new AEAW pins than can be muxed by separate.
+ When set to 0, those pins can be used for GPIOs. For our board,
+ we need gpio(10,11,12,13) to support the leds we have connected
+ on those pins.
+ */
+ davinci_cfg_reg(DM644X_AEAW0);
+ davinci_cfg_reg(DM644X_AEAW1);
+ davinci_cfg_reg(DM644X_AEAW2);
+ davinci_cfg_reg(DM644X_AEAW3);
+ davinci_cfg_reg(DM644X_AEAW4);
+ davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
+}
+
+static __init void davinci_ntosd2_irq_init(void)
+{
+ davinci_irq_init();
+}
+
+MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
+ /* Maintainer: Neuros Technologies <[hidden email]> */
+ .phys_io = IO_PHYS,
+ .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+ .boot_params = (DAVINCI_DDR_BASE + 0x100),
+ .map_io = davinci_ntosd2_map_io,
+ .init_irq = davinci_ntosd2_irq_init,
+ .timer = &davinci_timer,
+ .init_machine = davinci_ntosd2_init,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 84d3d26..2cd0081 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -368,6 +368,11 @@ MUX_CFG(DM644X, ATAEN_DISABLE, 0,   17,    1,  0, true)
 MUX_CFG(DM644X, HPIEN_DISABLE, 0,   29,    1,  0, true)
 
 MUX_CFG(DM644X, AEAW, 0,   0,     31,  31, true)
+MUX_CFG(DM644X, AEAW0, 0,   0,     1,  0, true)
+MUX_CFG(DM644X, AEAW1, 0,   1,     1,  0, true)
+MUX_CFG(DM644X, AEAW2, 0,   2,     1,  0, true)
+MUX_CFG(DM644X, AEAW3, 0,   3,     1,  0, true)
+MUX_CFG(DM644X, AEAW4, 0,   4,     1,  0, true)
 
 MUX_CFG(DM644X, MSTK, 1,   9,     1,  0, false)
 
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index d41ad16..b60c693 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -40,6 +40,11 @@ enum davinci_dm644x_index {
 
  /* AEAW functions */
  DM644X_AEAW,
+ DM644X_AEAW0,
+ DM644X_AEAW1,
+ DM644X_AEAW2,
+ DM644X_AEAW3,
+ DM644X_AEAW4,
 
  /* Memory Stick */
  DM644X_MSTK,
--
1.5.6.5


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[PATCH] Initial support for Neuros OSD2 platform.

Nori, Sekhar
Hello,

Couple of (styling related) comments below:

On Tue, Nov 10, 2009 at 16:52:00, Andrey Porodko wrote:

> The Neuros OSD 2.0 is the hardware component of the Neuros Open
> Internet Television Platform. Hardware is very close to Ti DM644X-EVM board.
> It has: DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
> USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
> Additionaly realtime clock, IR remote control receiver,
> IR Blaster based on MSP430 (firmware although is different
> from used in DM644X-EVM), internal ATA-6 3.5? HDD drive
> with PATA interface, two muxed red-green leds.
>
> For more information please refer to
>       http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
>
> Signed-off-by: Andrey Porodko <[hidden email]>

[...]

> diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
> new file mode 100644
> index 0000000..d0a1462
> --- /dev/null
> +++ b/arch/arm/mach-davinci/board-neuros-osd2.c
> @@ -0,0 +1,306 @@
> +/*
> + * Neuros Technologies OSD2 board support
> + *
> + * Modified from original 644X-EVM board support.
> + * 2008 (c) Neuros Technology, LLC.
> + * 2009 (c) Jorge Luis Zapata Muga <[hidden email]>
> + * 2009 (c) Andrey A. Porodko <[hidden email]>
> + *
> + * The Neuros OSD 2.0 is the hardware component of the Neuros Open
> + * Internet Television Platform. Hardware is very close to Ti

TI

> + * DM644X-EVM board. It has:
> + *   DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
> + *   USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
> + *   Additionaly realtime clock, IR remote control receiver,
> + *   IR Blaster based on MSP430 (firmware although is different
> + *   from used in DM644X-EVM), internal ATA-6 3.5? HDD drive
> + *   with PATA interface, two muxed red-green leds.
> + *
> + * For more information please refer to
> + *           http://wiki.neurostechnology.com/index.php/OSD_2.0_HD

License information is missing.

> + *
> + * 10/2009 Initial code with nand flash, fb, ide, ethernet, leds-gpio,
> + *   usb support.

No need of history in source files. git does it for us.

> + */
> +#include <linux/platform_device.h>
> +#include <linux/gpio.h>
> +

Unnecessary empty line

> +#include <linux/mtd/partitions.h>
> +
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +
> +#include <mach/dm644x.h>
> +#include <mach/i2c.h>
> +#include <mach/serial.h>
> +#include <mach/mux.h>
> +#include <mach/nand.h>
> +#include <mach/mmc.h>
> +#include <mach/usb.h>
> +
> +#define NEUROS_OSD2_PHY_MASK         (0x2)
> +#define NEUROS_OSD2_MDIO_FREQUENCY   (2200000) /* PHY bus frequency */

No need of parenthesis here...

> +
> +#define DAVINCI_CFC_ATA_BASE          0x01C66000
> +
> +#define DAVINCI_ASYNC_EMIF_CONTROL_BASE       0x01e00000
> +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
> +
> +#define LXT971_PHY_ID        (0x001378e2)
> +#define LXT971_PHY_MASK      (0xfffffff0)

... and here.

> +
> +#define      NTOSD2_AUDIOSOC_I2C_ADDR        0x18
> +#define      NTOSD2_MSP430_I2C_ADDR          0x59
> +#define      NTOSD2_MSP430_IRQ               2
> +

[...]

> +
> +static void __init
> +davinci_ntosd2_map_io(void)

This stands out since other function definitions aren?t broken up
like this.

> +{
> +     dm644x_init();
> +}
> +
> +/*
> + I2C initilization

Spelling.. :)

> +*/
> +static struct davinci_i2c_platform_data ntosd2_i2c_pdata = {
> +     .bus_freq       = 20 /* kHz */,
> +     .bus_delay      = 100 /* usec */,
> +};
> +

[...]

> +
> +static __init void davinci_ntosd2_init(void)
> +{
> +     struct clk *aemif_clk;
> +     struct davinci_soc_info *soc_info = &davinci_soc_info;
> +
> +     aemif_clk = clk_get(NULL, "aemif");
> +     clk_enable(aemif_clk);
> +
> +     if (HAS_ATA) {
> +             if (HAS_NAND)
> +                     pr_warning("WARNING: both IDE and Flash are "
> +                             "enabled, but they share AEMIF pins.\n"
> +                             "\tDisable IDE for NAND/NOR support.\n");
> +             davinci_cfg_reg(DM644X_HPIEN_DISABLE);
> +             davinci_cfg_reg(DM644X_ATAEN);
> +             davinci_cfg_reg(DM644X_HDIREN);
> +             platform_device_register(&ide_dev);
> +     } else if (HAS_NAND) {
> +             davinci_cfg_reg(DM644X_HPIEN_DISABLE);
> +             davinci_cfg_reg(DM644X_ATAEN_DISABLE);
> +
> +             /* only one device will be jumpered and detected */
> +             if (HAS_NAND)
> +                     platform_device_register(
> +                                     &davinci_ntosd2_nandflash_device);
> +     }
> +
> +     platform_add_devices(davinci_ntosd2_devices,
> +                             ARRAY_SIZE(davinci_ntosd2_devices));
> +
> +     /* Initialize I2C interface specific for this board */
> +     ntosd2_init_i2c();
> +
> +     davinci_serial_init(&uart_config);
> +     dm644x_init_asp(&dm644x_ntosd2_snd_data);
> +
> +     soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK;
> +     soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;
> +
> +     davinci_setup_usb(1000, 8);
> +     /* Mux the pins to be GPIOS, VLYNQEN is already done at startup */
> +     /* The AEAWx. are five new AEAW pins than can be muxed by separate.
> +      When set to 0, those pins can be used for GPIOs. For our board,
> +      we need gpio(10,11,12,13) to support the leds we have connected
> +      on those pins.
> +      */

Please follow the preferred multi-line commenting described
in Documentation/CodingStyle chapter 8.

Thanks,
Sekhar

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[PATCH] Initial support for Neuros OSD2 platform.

A. Porodko
Nori, Sekhar wrote:
> Hello,
>
> Couple of (styling related) comments below:
>
>  
Fixed. Seems this is a long road to mainstream ;-)
...cut...

--
Best regards
Andrey A. Porodko