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Patch 1/2 Inital support of Neuros OSD2 (third attempt)

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Patch 1/2 Inital support of Neuros OSD2 (third attempt)

Kevin Hilman
"A. Porodko" <[hidden email]> writes:

> Initial support for Neuros OSD2 (DM644X based) board.

Please add a detailed changelog.  Some references to the board would
be helpful, as well as a summary of the features of the board being
supported in this patch: NAND, IDE, MMC, etc.

Also, please report how this was tested and on what trees.  While this
patch applies to davinci git master, it doesn't compile so I have to
assume it was not runtime tested either.

I would also recommend using git-format-patch to better format
your patches and git-send-email to send them.

Also, please run this patch through checkpatch (see
scripts/checkpatch.pl) in the kernel source.  It currently reports:

    total: 13 errors, 11 warnings, 372 lines checked

A few more comments below, but the above problems are enough to prevent
me from doing a more thorough review.

>
> diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
> index be92240..ac0c349 100644
> --- a/arch/arm/mach-davinci/Kconfig
> +++ b/arch/arm/mach-davinci/Kconfig
> @@ -136,6 +136,13 @@ config MACH_DAVINCI_DA850_EVM
>   help
>    Say Y here to select the TI DA850/OMAP-L138 Evaluation Module.
>  
> +config MACH_NEUROS_OSD2
> + bool "Neuros OSD2 Open Set Top Box"
> + depends on ARCH_DAVINCI_DM644x
> + help
> +  Configure this option to specify the whether the board used
> +  for development is a Neuros OSD2 Open Set Top Box.
> +

Please group this with the other dm644x based boards.

>  config DA850_UI_EXP
>   bool "DA850/OMAP-L138 UI (User Interface) board expander configuration"
>   depends on MACH_DAVINCI_DA850_EVM
> diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
> index be629c5..5dcb3b0 100644
> --- a/arch/arm/mach-davinci/Makefile
> +++ b/arch/arm/mach-davinci/Makefile
> @@ -29,6 +29,6 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o
>  obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
>  obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
>  obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
> -
> +obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o

ditto. place after the SFFSDR

>  # Power Management
>  obj-$(CONFIG_CPU_FREQ) += cpufreq.o
> diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
> new file mode 100644
> index 0000000..51784c3
> --- /dev/null
> +++ b/arch/arm/mach-davinci/board-neuros-osd2.c
> @@ -0,0 +1,352 @@
> +/*
> + * Neuros Technologies OSD2 board support
> + *
> + * Modified from original EVM board support (see below).
> + * ----------------------------------------- 03/06, 2008 <mgao@neuros>
> + * 2008 (c) Neuros Technology, LLC.
> + * 2009 (c) Jorge Luis Zapata Muga <[hidden email]>
> + * 2009 (c) Andrey A. Porodko <[hidden email]>
> + *
> + * Author: Kevin Hilman, MontaVista Software, Inc. <[hidden email]>

Hmm, I had nothing to do with this code, nor do I work for MV
(anymore.)

If it was based on code originally written by me (or anyone else) that
should be stated rather than stating authorship.

> + */
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/platform_device.h>
> +#include <linux/gpio.h>
> +#include <linux/leds.h>
> +#include <linux/memory.h>
> +
> +#include <linux/i2c.h>
> +#include <linux/i2c/at24.h>

This one is unused.

> +#include <linux/i2c/neuros_osd2_msp.h>

This file doesn't exist and will cause compile error.

> +#include <linux/etherdevice.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/mtd/physmap.h>
> +#include <linux/io.h>
> +#include <linux/phy.h>
> +#include <linux/clk.h>
> +
> +#include <asm/setup.h>
> +#include <asm/mach-types.h>
> +
> +#include <asm/mach/arch.h>
> +#include <asm/mach/map.h>
> +#include <asm/mach/flash.h>
> +
> +#include <mach/dm644x.h>
> +#include <mach/common.h>
> +#include <mach/i2c.h>
> +#include <mach/serial.h>
> +#include <mach/mux.h>
> +#include <mach/psc.h>
> +#include <mach/nand.h>
> +#include <mach/mmc.h>
> +#include <mach/emac.h>
> +#include <mach/common.h>
> +
> +#define NEUROS_OSD2_PHY_MASK (0x2)
> +#define NEUROS_OSD2_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
> +
> +#define DAVINCI_CFC_ATA_BASE  0x01C66000
> +
> +#define DAVINCI_ASYNC_EMIF_CONTROL_BASE   0x01e00000
> +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
> +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
> +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE  0x06000000
> +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE  0x08000000

CE[1..3] are unused.

> +#define LXT971_PHY_ID (0x001378e2)
> +#define LXT971_PHY_MASK (0xfffffff0)
> +
> +#define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
> +
> +#define NTOSD2_PINMUX1 IO_ADDRESS(0x01C40004)

Should't be needed.  Access to mux regs should be using mux API.

> +#define NTOSD2_PWM0_PCR IO_ADDRESS(0x01C22004)
> +#define NTOSD2_PWM0_CFG IO_ADDRESS(0x01C22008)
> +#define NTOSD2_PWM0_START IO_ADDRESS(0x01C2200C)
> +#define NTOSD2_PWM0_PER IO_ADDRESS(0x01C22014)
> +#define NTOSD2_PWM0_PH1D IO_ADDRESS(0x01C22018)

Please drop usage of IO_ADDRESS() which is deprecated.  Please
ioremap() the area and use the normal read/write accessors.

> +/* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
> + * 2048 blocks in the device, 64 pages per block, 2048 bytes per
> + * page.
> + */
> +
> +#define NAND_BLOCK_SIZE      SZ_128K
> +
> +struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
> + {
> + /* UBL (a few copies) plus U-Boot */
> + .name = "bootloader",
> + .offset = 0,
> + .size = 15 * NAND_BLOCK_SIZE,
> + .mask_flags = MTD_WRITEABLE, /* force read-only */
> + }, {
> + /* U-Boot environment */
> + .name = "params",
> + .offset = MTDPART_OFS_APPEND,
> + .size = 1 * NAND_BLOCK_SIZE,
> + .mask_flags = 0,
> + }, {
> + /* Kernel */
> + .name = "kernel",
> + .offset = MTDPART_OFS_APPEND,
> + .size = SZ_4M,
> + .mask_flags = 0,
> + }, {
> + /* File System */
> + .name = "filesystem",
> + .offset = MTDPART_OFS_APPEND,
> + .size = MTDPART_SIZ_FULL,
> + .mask_flags = 0,
> + }
> + /* A few blocks at end hold a flash Bad Block Table. */
> +};
> +
> +static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
> + .parts = davinci_ntosd2_nandflash_partition,
> + .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
> + .ecc_mode = NAND_ECC_HW,
> + .options = NAND_USE_FLASH_BBT,
> +};
> +
> +static struct resource davinci_ntosd2_nandflash_resource[] = {
> + {
> + .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
> + .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
> + .flags = IORESOURCE_MEM,
> + }, {
> + .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
> + .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
> + .flags = IORESOURCE_MEM,
> + },
> +};
> +
> +static struct platform_device davinci_ntosd2_nandflash_device = {
> + .name = "davinci_nand",
> + .id = 0,
> + .dev = {
> + .platform_data = &davinci_ntosd2_nandflash_data,
> + },
> + .num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
> + .resource = davinci_ntosd2_nandflash_resource,
> +};
> +
> +static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
> +
> +static struct platform_device davinci_fb_device = {
> + .name = "davincifb",
> + .id = -1,
> + .dev = {
> + .dma_mask = &davinci_fb_dma_mask,
> + .coherent_dma_mask      = DMA_BIT_MASK(32),
> + },
> + .num_resources = 0,
> +};
> +
> +static struct resource ide_resources[] = {
> + {
> + .start          = DAVINCI_CFC_ATA_BASE,
> + .end            = DAVINCI_CFC_ATA_BASE + 0x7ff,
> + .flags          = IORESOURCE_MEM,
> + },
> + {
> + .start          = IRQ_IDE,
> + .end            = IRQ_IDE,
> + .flags          = IORESOURCE_IRQ,
> + },
> +};
> +
> +static u64 ide_dma_mask = DMA_BIT_MASK(32);
> +
> +static struct platform_device ide_dev = {
> + .name           = "palm_bk3710",
> + .id             = -1,
> + .resource       = ide_resources,
> + .num_resources  = ARRAY_SIZE(ide_resources),
> + .dev = {
> + .dma_mask = &ide_dma_mask,
> + .coherent_dma_mask      = DMA_BIT_MASK(32),
> + },
> +};
> +
> +static struct snd_platform_data dm644x_ntosd2_snd_data;
> +
> +static struct gpio_led ntosd2_leds[] = {
> + { .name = "led1_green", .gpio = GPIO(10), },
> + { .name = "led1_red",   .gpio = GPIO(11), },
> + { .name = "led2_green", .gpio = GPIO(12), },
> + { .name = "led2_red",   .gpio = GPIO(13), },
> +};
> +
> +static struct gpio_led_platform_data ntosd2_leds_data = {
> + .num_leds = ARRAY_SIZE(ntosd2_leds),
> + .leds = ntosd2_leds,
> +};
> +
> +static struct platform_device ntosd2_leds_dev = {
> + .name = "leds-gpio",
> + .id   = -1,
> + .dev = {
> + .platform_data = &ntosd2_leds_data,
> + },
> +};
> +
> +
> +static struct platform_device *davinci_ntosd2_devices[] __initdata = {
> + &davinci_fb_device,
> + &ntosd2_leds_dev,
> +};
> +
> +static struct davinci_uart_config uart_config __initdata = {
> + .enabled_uarts = (1 << 0),
> +};
> +
> +static void __init
> +davinci_ntosd2_map_io(void)
> +{
> + dm644x_init();
> +}
> +
> +/*
> + I2C initilization
> +*/
> +static struct davinci_i2c_platform_data ntosd2_i2c_pdata = {
> + .bus_freq = 20 /* kHz */,
> + .bus_delay = 100 /* usec */,
> +};
> +
> +static struct i2c_board_info __initdata ntosd2_i2c_info[] =  {
> + { /* MSP430 interface */
> + I2C_BOARD_INFO("neuros_osd2_msp", NTOSD2_MSP430_I2C_ADDR),
> + },

Drop this MSP interface until the driver is submitted.

> + { /* TLV320AIC32 interface */

This comment isn't necessary.

> + I2C_BOARD_INFO("tlv320aic3x", NTOSD2_AUDIOSOC_I2C_ADDR ),
> + },
> + /* ALSO:
> + * - ?
> + */

Drop this unhelpful comment.

> +};
> +
> +static void __init ntosd2_init_i2c(void)
> +{
> + davinci_init_i2c(&ntosd2_i2c_pdata);
> + gpio_request(NTOSD2_MSP430_IRQ,ntosd2_i2c_info[0].type);
> + gpio_direction_input(NTOSD2_MSP430_IRQ);
> + ntosd2_i2c_info[0].irq = gpio_to_irq(NTOSD2_MSP430_IRQ);
> + i2c_register_board_info(1, ntosd2_i2c_info, ARRAY_SIZE(ntosd2_i2c_info));
> +}
> +
> +static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
> + .wires = 4,
> + .version = MMC_CTLR_VERSION_1
> +};
> +
> +
> +/*  
> + Prepare 38KHz generator for future use by neuros_osd2_irblaster driver
> +*/
> +static void ntosd2_init_38khz(void)
> +{
> + unsigned long value;
> +
> + value = __raw_readl(NTOSD2_PINMUX1) | (1<<4);
> + __raw_writel(value,NTOSD2_PINMUX1); /*set gio45/PWM0 pin works as PWM0 */

Hmm, can't use use mux API?

> + __raw_writel(1,NTOSD2_PWM0_PCR);
> + value = __raw_readl(NTOSD2_PWM0_CFG) & ~2;
> + __raw_writel(value,NTOSD2_PWM0_CFG); /* clear PWM0 mode */
> + value = __raw_readl(NTOSD2_PWM0_CFG) | 2;
> + __raw_writel(value,NTOSD2_PWM0_CFG); /* set PWM0 contiguous mode */
> + /* PWM0_PER+1=PWM0_PH1D*2 */
> + /* PWM config PWM 38kHz PER=709 PH1D=355*/
> + __raw_writel(709,NTOSD2_PWM0_PER);
> + __raw_writel(355,NTOSD2_PWM0_PH1D);
> + __raw_writel(1,NTOSD2_PWM0_START);
> +}

I suggest dropping the PWM init from this patch and adding it in a
separate patch with a clear description of how it is connected and
configured.

> +
> +#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
> + defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
> +#define HAS_ATA 1
> +#else
> +#define HAS_ATA 0
> +#endif
> +
> +#if defined(CONFIG_MTD_NAND_DAVINCI) || \
> + defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
> +#define HAS_NAND 1
> +#else
> +#define HAS_NAND 0
> +#endif
> +
> +static __init void davinci_ntosd2_init(void)
> +{
> + struct clk *aemif_clk;
> + struct davinci_soc_info *soc_info = &davinci_soc_info;
> +
> + aemif_clk = clk_get(NULL, "aemif");
> + clk_enable(aemif_clk);
> +
> + if (HAS_ATA) {
> + if (HAS_NAND)
> + pr_warning("WARNING: both IDE and Flash are "
> + "enabled, but they share AEMIF pins.\n"
> + "\tDisable IDE for NAND/NOR support.\n");
> + davinci_cfg_reg(DM644X_HPIEN_DISABLE);
> + davinci_cfg_reg(DM644X_ATAEN);
> + davinci_cfg_reg(DM644X_HDIREN);
> + platform_device_register(&ide_dev);
> + } else if (HAS_NAND) {
> + davinci_cfg_reg(DM644X_HPIEN_DISABLE);
> + davinci_cfg_reg(DM644X_ATAEN_DISABLE);
> +
> + /* only one device will be jumpered and detected */
> + if (HAS_NAND) {
> + platform_device_register(&davinci_ntosd2_nandflash_device);
> + }
> + }
> +
> + platform_add_devices(davinci_ntosd2_devices,
> + ARRAY_SIZE(davinci_ntosd2_devices));
> +
> + /* Initialize I2C interface specific for this board */
> + ntosd2_init_i2c();
> +
> + davinci_serial_init(&uart_config);
> + dm644x_init_asp(&dm644x_ntosd2_snd_data);
> +
> + soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK;
> + soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;
> +
> + setup_usb(500, 8);
> + /* Mux the pins to be GPIOS, VLYNQEN is already done at startup */
> + davinci_cfg_reg(DM644X_AEAW0);
> + davinci_cfg_reg(DM644X_AEAW1);
> + davinci_cfg_reg(DM644X_AEAW2);
> + davinci_cfg_reg(DM644X_AEAW3);
> + davinci_cfg_reg(DM644X_AEAW4);
> + davinci_cfg_reg(DM644X_PWM0);
> + davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
> + ntosd2_init_38khz(); /* init IR blaster 38kHz generator */
> +}
> +
> +static __init void davinci_ntosd2_irq_init(void)
> +{
> + davinci_irq_init();
> +}
> +
> +MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
> + /* Maintainer: Neuros Technologies <[hidden email]> */
> + .phys_io      = IO_PHYS,
> + .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
> + .boot_params  = (DAVINCI_DDR_BASE + 0x100),
> + .map_io      = davinci_ntosd2_map_io,
> + .init_irq     = davinci_ntosd2_irq_init,
> + .timer      = &davinci_timer,
> + .init_machine = davinci_ntosd2_init,
> +MACHINE_END

Kevin

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